SPM结构上冗余读延迟写优化的设计与实现

DESIGNING REDUNDANT READ AND DELAY WRITE OPTIMISATION ON SPM ARCHITECTURE AND ITS IMPLEMENTATION

随着微处理器架构的发展,将片上SRAM组织成SPM这种软件管理的非cache结构成为众多处理器的选择。SPM结构的特点是实现简单,访问延迟低、带宽高。要有效利用有限的片上SPM空间提升程序性能,必须由用户显式进行数据的布局和传送,或者由编译器进行高效的自动访存优化。冗余读延迟写优化从循环中多个主存访问之间的关联性出发,自动进行了数据传送和缓存优化,提高了SPM上的数据重用率。经过测试,可以有效提升程序性能。

With the development of microprocessor architecture, non-cache structure becomes the option of many processors which configures the on-chip SRAM memory as the software-managed seratehpad memory （SPM）. The features of SPM structure include simple in implementation, low access latency and high bandwidth. For effectively utilising the limit on-chip SPM space to improve program＇ s performance, it has to either to distribute and transmit data explicitly by the user or to efficiently optimise the automatic memory access by the compiler. As to the redundant read and delay write optimisation, proceeding from the association between multiple memories access in circulation, it carries out data transmission and cache optimisation automatically, and improves the data reuse rate on SPM. After test, it is able to effectively raise the performance of the program.