基于FPGA的DVB-S2 LDPC编码器的设计与实现

Design of LDPC Encoder in DVB-S2 Based on FPGA

低密度奇偶校验码(LDPC)由于具有极其出色的比特纠错性能而被第2代卫星数字视频广播标准(DVB-S2)所采用。为满足宽带多媒体系统高吞率的应用需求,针对DVB-S2标准提供的LDPC码字结构,提出了利用FPGA上的RAM存储单元存储校验比特的方法,校验比特计算模块采用部分并行计算结构,据此设计了基于FPGA的LDPC编码器实现方案。该方案已经在EP3C120F484I7 CycloneⅢAtera FPGA上实现,经过测试吞吐量可达2.6 Gb/s。

Due to their excellent bit-error-rate performance,Low Density Parity Check（ LDPC） codes have been adopted by the second Digital Video Satellite Broadcast Standard（ DVB-S2）. In order to meet the application requirement of broadband multimedia satellite system,this paper develops a technique using RAM storage element on FPGA chip to store the check bits of LDPC codes and a kind of encoder structure of LDPC employed by DVB-S2. The architecture explores the periodic structure of the adopted codes by performing on the flypartial-parallel computation of the parity check bits. The design has been implemented with both serial and parallel input on a EP3C120F484I7 Cyclone Ⅲ Atera FPGA. The throughput is tested in 2. 6 Gb / s successfully.