面向序列密码的比特级抽取指令研究与设计

Research and Design of Bit-Level Extraction Instruction for Stream Cipher

针对通用处理器中比特级操作效率低下的问题,提出了一种面向序列密码算法的比特级抽取指令,并构造了与之相应的硬件单元。将该单元在CMOS 0.13μm工艺下完成综合,同时通过NIOSⅡ扩展指令的方式把设计的专用指令加入到处理器中进行了性能评估。结果表明:该指令的加入并不影响处理器的处理器频率,与未经扩展指令的嵌入式RSIC处理器相比,完成相同的抽取操作指令条数从250条减少为1条,有效地提升了序列密码算法的处理性能。

Current microprocessors do not directly support bit level arbitrary permutations when implemented with software instrucions. This paper proposes a new bit level instrucion named ＂extract＂for stream ciphers and presents a corresponding bit level functional hardware which synthesizes and is optimized with CMOS 0. 13μm technology. Moreover,the instrucion is also added into the ISA of NIOSⅡ microprocessors. The result shows that adding the instrucion can improve the stream cipher effectively without hindering the maximum frequency of general-purpose processors,and the number of the extract operations decreases from 250 to 1.