一种2.5Gb/s LVDS接收器设计

Design of a 2.5Gb/s LVDS Receiver

基于SMIC 0.18μm 1P6M标准CMOS工艺,设计了一种2.5Gb/s LVDS接收器电路。仿真结果表明,所设计的LVDS电路参数符合LVDS标准,LVDS接收器的输出信号上升沿抖动约为0.76ps,有效版图面积约为(83×44)μm2,能应用于高速数据接口。

A 2.5Gb/s LVDS receiver circuit was designed based on the SMIC 0.18μm 1P6 Mstandard CMOS technology.The simulation results showed that the parameters of the LVDS receiver met the LVDS standard.The rising edge jitter of the output signal of the LVDS receiver was about 0.76 ps,and the area of the layout was about（83×44）μm2.The LVDS receiver circuit can be applied to high-speed data interface.