一种基于ASIP结构的LDPC译码器芯片设计

Design of LDPC Decoder Chip Based on ASIP Architecture

针对IEEE 802.11n标准中LDPC码多码率、多码长的特点,提出了一种基于ASIP架构的LDPC译码器设计方案。该译码器采用优化的分层译码算法、11级流水线技术以及基于ASIP结构的微指令技术,实现了4种不同码率、3种不同码长的LDPC译码功能。采用TSMC 0.18μm CMOS工艺进行物理实现,该译码器芯片面积为3.65 mm2。测试结果表明,该设计满足IEEE802.11n标准的译码要求。

For the characteristics of the multi-rate and multi-size for LDPC codes specified in the IEEE 802.11 n standard,a design scheme of LDPC decoder based on ASIP architecture was proposed.The decoder adopted layered belief propagations（LBP）algorithm optimized by normalized min-sum（NMS）algorithm,the eleven-stage pipeline technology and the micro instruction technology based on ASIP architecture,so the LDPC decoding functions were realized that could support the LDPC codes with four different code rates and three different code sizes.The proposed design was implemented in TSMC 0.18μm CMOS technology,and the chip area was 3.65mm2.The test results showed that the proposed design met the decoding requirements of the IEEE 802.11 nstandard.