受摆率约束的缓冲器插入设计优化方法

Slew Constrained Optimal Buffer Insertion Method

随着VLSI集成度的提高,缓冲器插入技术作为一种互连优化方法,在系统设计中得到了广泛的应用。提出一种针对片上互连网络的缓冲器插入方法,求解在摆率约束下的缓冲器最优插入问题。该方法由两阶段算法组成,首先对待优化互连线网进行分段,以求解可行的缓冲器插入位置集合,其次在所求得的上述位置集合中求解摆率约束条件下的最小代价缓冲器插入问题。在0.13μm CMOS工艺下进行电路设计,实验结果表明,相较于延时最优缓冲器插入方法,该方法所得优化结果能够满足实际电路的摆率约束,同时获得最小超过30%的面积改善比率。

With the improvement of VLSI’s integration,buffer insertion has been widely used in system design as an interconnect optimization method.A method was proposed to address the slew constrained optimal buffer insertion problem.The proposed method took advantages of both analytical method and dynamic programming,and produced a two-stage optimization flow.Firstly,it divided each wire of the routing trees into small segments to find candidate buffer locations based on analytical methods’results.Secondly,it solved the slew-constrained optimal-cost buffer insertion problem by using the modified dynamic programming.An industrial 0.13 μm standard CMOS process circuit design results showed that the proposed method produced circuits that could satisfy the global slew constraint.Furthermore,it achieved at least 30% area reduction of inserted buffers compared to the timing-driven buffer insertion method.