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基于FSMC总线的多处理器并行计算系统的研究与设计

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摘要 嵌入式系统在图像处理、空间计算等领域越来越广泛,如何在功耗、成本和计算能力三个主要方面取得平衡,利用多核和多处理器系统以并行计算方式提高嵌入式系统计算能力是一种有效的解决方案。意法半导体公司基于CortexM3架构的STM32系列提供FSMC总线,利用该总线系统设计一种特殊的SMP多处理器系统并进行图像算法并行化研究。实验结果分析表明,在该嵌入式多处理器平台上配合并行算法能够成倍提图像算法的运行性能。
出处 《福建电脑》 2014年第5期35-37,共3页 Journal of Fujian Computer
基金 湖北工程学院新技术学院学生科研重点项目 湖北工程学院自然科学研究项目(Z2013016) 湖北省青年教师深入企业行动资助项目(XD2012392)
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参考文献12

  • 1McNairy C, Bhatia R. Montecito: A dual-core, dual-thread i- tanium processor. IEEE Micro, 2005, 25(2): 10-20.
  • 2KaUa R.IBM power5 chip: A dual-core multithreaded proces- sor. IEEE Micro, 2004, 24(20):40-47.
  • 3Mladen B, Hans JS, Peter P. Multicore system-onchip archi- tecture for MPEG-4 streaming video. IEEE Transactions on Cir- cuits and Systems for Video Technology ,2002,12(8):688-699.
  • 4Lee Trong-Yen.Fan Yang-Hsin,Cheng Yu-Minetal. Hard- ware oriented partition for embedded multiprocessor FPGA sys- tem// Proceedings of the 2the International Conference on Inno- vative Computing, Information and Control (ICICIC 2007).Ku- mamoto, Japan ,2007.
  • 5Toledo F,Martirlez J, Ferrandez J. FPGA-based platform for image and video processing embedded systems//Proceedings of the 2007 3rd Southern Conference on Programmable Logic (SPL' 07). 2007:171-176.
  • 6Li Yong,Wang Zhi-Ying,Zhao Xue-Mi et al. Designg of a low-power embedded processor architecture using asynchronous function units. Lecture Notes In Computer Science,2008:354-363.
  • 7全巍,文梅,伍楠,杨乾明,张春元.高性能异构多处理器平台及其应用[J].计算机工程与科学,2011,33(1):60-65. 被引量:4
  • 8颜露新,张天序,邹胜,钟胜.用FPGA实现互联的多DSP并行系统结构[J].系统工程与电子技术,2005,27(10):1757-1759. 被引量:4
  • 9王洁,张淑燕,刘涛,季振洲,胡铭曾.基于FPGA的嵌入式多核处理器及SUSAN算法并行化[J].计算机学报,2008,31(11):1995-2004. 被引量:5
  • 10吕雷,王明昌,秦金明.基于FPGA的多DSP红外实时图像处理系统[J].现代电子技术,2010,33(22):97-99. 被引量:5

二级参考文献47

  • 1甘旭军,李平康,杜秀霞.多DSP并列高速信号处理器的设计与实现[J].仪器仪表学报,2002,23(z2):574-576. 被引量:9
  • 2周志权,刘昕.基于FPGA的实时图像预处理系统的设计[J].华北航天工业学院学报,2005,15(3):20-22. 被引量:3
  • 3陈镇.中值滤波器的FPGA实现方案[J].红外,2005,26(10):17-21. 被引量:6
  • 4Mladen B, Hans J S, Peter P. Multicore system-onchip architecture for MPEG-4 streaming video. IEEE Transactions on Circuits and Systems for Video Technology, 2002, 12(8) : 688-699
  • 5Lee Trong-Yen, Fan Yang-Hsin, Cheng Yu-Min et al. Hardware-oriented partition for embedded multiprocessor FPGA systems//Proceedings of the 2th International Conference on Innovative Computing, Information and Control (ICICIC 2007). Kumamoto, Japan, 2007
  • 6Toledo F, Martinez J, Ferrandez J. FPGA-based platform for image and video processing embedded systems//Proceedings of the 2007 3rd Southern Conference on Programmable Logic (SPL'07). Mar del Plata, Argentina, 2007:171-176
  • 7Hofmann Andreas, Waldschmidt Klaus. SDVMR: A scalable firmware for FPGA-based multi-core Systems-on-Chip// Proceedings- IEEE Computer Society Annual Symposium on VLSI: Trends in VLSI Technology and Design, ISVLSI. Montpellier, France, 2008:387-392
  • 8Noseworthy Joshua, Leeser Miriam. Efficient communication between the embedded processor and the reconfigurable logic on an FPGA. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2008, 16(8) : 1083-1090
  • 9Kleinosowski A, Lilja D J. MinneSPEC: A new SPEC benchmark workload for simulation-based computer architecture research. University of Minnesota ARCTIC Lab, 2002-10
  • 10Levy Markus. Keynote 1: Using EEMBC benchmarks to understand processor behavior in embedded applications//Proceedings of the 1st International Conference on High Performance Embedded Architectures and Compilers (HiPEAC 2005). Lecture Notes in Computer Science 3793. Barcelona, Spain, 2005:3-4

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