超低功耗逐次逼近寄存器型模数转换器的设计

Design of Ultra Low Power SAR ADC

采用逐次逼近方式设计了一个12 bit的超低功耗模数转换器(ADC)。为减小整个ADC的芯片面积、功耗和误差,提高有效位数(ENOB),在整个ADC的设计过程中采用了一种改进的分段电容数模转换器(DAC)阵列结构。重点考虑了同步时序产生电路结构,对以上两个模块的版图设计进行了精细的布局。采用0.18μm CMOS工艺,该ADC的信噪比(SNR)为72 d B,有效位数(ENOB)为11.7 bit,该ADC的芯片面积只有0.36 mm2,典型的功耗仅为40μW,微分非线性误差小到0.6 LSB、积分非线性误差只有0.63 LSB。整个ADC性能达到设计要求。

A 12 bit ultra low power analog to digital converter（ ADC） was designed by using successive approximation method. To reduce the chip size,power and errors and improve effective number of bits（ ENOB）,an improved segmentation capacitance digital to analog converter（ DAC） array structure was adopted during the whole design process of ADC. The structure of synchronization timing generation circuit was considered,and the layouts of these two modules were arranged narrowly. Based on 0. 18 μm CMOS process, the signal noise ratio（ SNR） of the ADC is 72 d B, and ENOB is11. 7 bit. The total chip size is only 0. 36 mm2,the typical power is only 40 μW,the differential nonlinearity error is 0. 6 LSB,and the integral non-linearity error is 0. 63 LSB. The performance requirement of the ADC was achieved.