一种组合延迟槽和预译码技术的新型分支预测器

A Novel Branch Predictor Combining with Delay Slot and Pre-decode Techniques

分支预测是现代微处理器普遍用于提高指令吞吐率的关键技术,随着处理器性能需求的不断增长,分支预测结构越来越复杂,其功耗问题也日益突出.针对SPARC V8架构嵌入式处理器的结构特点和应用需求,设计了一种基于延迟槽的动态分支预测器,以此来提高处理器的预测性能;另外,通过分析动态预测器的几种设计空间,提出采用预译码机制来消除无效访问的电路结构,从而降低预测器的功耗开销.该设计在SMIC 0.13μm工艺下实现,分支预测准确度相比于之前的静态算法提高了21%,动态预测器本身的功耗降低了58%,而整个处理器的面积仅增加1.73%.结果表明,这种组合延迟槽和预译码技术的分支预测思想对SPARC处理器的性能和功耗都达到了很好的优化效果.

Branch prediction is a critical technique for modem processors to improve instruction throughput. With increasing require- ments on processor performance, the structure of branch predictor becomes more and more complex, and so its power consumption is extremely prominent. Aiming at the characteristics and applications of the SPARC V8 embedded processor, this paper proposed a dy- namic branch predictor based on delay slot to improve the processor＇s performance. In addition,it analyzed several design methods for this dynamic predictor, and used pre-decode circuit for eliminating invalid accesses to the predictor in order to reduce the power of the predictor. This design has been implemented in SMIC 0. 13 μm technology, and the experimental results show that the prediction accu- racy is improved by 21% compared with the original static prediction method, that the power of the dynamic predictor is reduced by 58%, and that the chip area for the whole processor is increased by only 1.73%. As a result,this branch predictor combining with de- lay slot and pre-decode techniques brings an outstanding effect on the performance and power optimization for the SPARC processor.