基于FPGA的AES加密算法功耗研究

The research of the power consumption of the AES encryption algorithm based on FPGA

AES(Advanced Encryption Standard)是美国国家标准技术研究所NIST旨在取代DES的21世纪的加密标准.详细介绍了AES加密的算法原理,实现了基于FPGA平台AES加密算法的设计与功能仿真.从静态和动态两方面分析了功耗的产生原因,研究了基于FPGA平台的AES加密算法降低功耗的问题,以及随着时钟频率的增加,系统功耗的变化趋势.算法模块占用逻辑资源少,加密效率高,并在保证安全性,和满足应用需求的前提下,实现了平衡数据处理速度和系统功耗这两个重要参数的目的.

AES（Advanced Encryption Standard） is an Encryption Standard proposed by American national standards institute of technology NIST to replace DES Encryption Standard in the 21 st century. The principle of AES encryption algorithm was introduced in detail; the design and function simulation of the AES encryption algorithm based on FPGA platform were completed. Reducing power consumption of the AES encryption algorithm based on FPGA was discussed.The causes of the power consumption were analysed from static and dynamic aspects. With the increase of clock frequency,the tendency of the system power consumption was studied, too. Algorithm module occupies less logical resources, yet has high efficiency in encryption. The purpose of balancing the two important parameters-data processing speed and power consumption has been reached upon the preconditions of guaranteeing the security and meeting the demand of many applications.