期刊文献+

考虑场板边缘效应的SOI-pLDMOS表面电场模型及器件优化设计

Surface electrical field model of SOI-pLDMOS considering edge effect of field plate and optimization design
下载PDF
导出
摘要 针对带有栅极场板的绝缘体上硅p型横向双扩散场效应晶体管(SOI-p LDMOS),提出了一种新型表面电场解析模型.相比于传统模型,该模型充分考虑了场板边缘效应对电场分布的影响,验证结果显示新模型能更好地符合Medici数值仿真结果.此外,基于所建立的器件表面电场模型,研究了栅极场板长度(包括多晶硅场板和金属场板)及漂移区掺杂浓度对器件表面电场分布和击穿特性的影响,进而对SOI-p LDMOS进行了优化设计.流片测试表明,所建立的新型表面电场解析模型能够很好地指导器件参数设计,实现了器件耐压和导通电阻的最佳折中. A new surface electrical field analytical model is presented for the p-type lateral double diffusion MOS( metal-oxide-semiconductor) transistor based on silicon on insulator( SOI-pLDMOS) with gate field plate. Compared with the traditional analytical model,the proposed model fully considers the influence of the edge effect of field plate upon the electrical field distribution. The results show that the presented model accords with the Medici simulations better. In addition,based on the new analytical model,the effects of the length of the gate field plate( including the polysilicon field plate and metal field plate) and the concentration of p-drift on electrical field distributions and breakdow n characteristics are researched. Also,a SOI-p LDMOS is optimally designed. The test results demonstrate that the new surface electrical field analytical model can guide the design of device parameters and realize the best compromise betw een the breakdow n voltage and on-resistance.
出处 《东南大学学报(自然科学版)》 EI CAS CSCD 北大核心 2015年第2期214-218,共5页 Journal of Southeast University:Natural Science Edition
基金 港澳台科技合作专项资助项目(2014DFH10190) 江苏省青蓝工程资助项目 东南大学研究生科研基金资助项目(YBPY1403)
关键词 解析模型 表面电场 SOI-pLDMOS 边缘效应 analytical model surface field SOI-pLDMOS edge effect
  • 相关文献

参考文献12

  • 1万维俊,刘斯扬,孙虎,孙伟锋.高栅压低漏压条件下FG-pLEDMOS的热载流子退化机理[J].东南大学学报(自然科学版),2012,42(1):25-28. 被引量:1
  • 2Zhou Kun, Luo Xiaorong, Xu Qing, et al. A RESURF enhanced p-channel trench SOI LDMOS with ultral low specific on-resistance [J]. IEEE Transactions on Electron Devices, 2014, 61(7): 2466-2472.
  • 3Miyoshi T, Tominari T, Fujiwara H, et al. Design of a reliable p-channel LDMOSFET with RESURF technology [J]. IEEE Transactions on Electron Devices, 2014, 61(5): 1451-1456.
  • 4郑维山,孙虎,刘斯扬,孙伟锋.pLEDMOS导通电阻及阈值电压的热载流子退化[J].东南大学学报(自然科学版),2011,41(3):522-525. 被引量:2
  • 5Nandi A, Saxena A K, Dasgupta S. Analytical modeling of a double gate MOSFET considering source/drain lateral Gaussian doping profile [J]. IEEE Transactions on Electron Devices, 2013, 60(11): 3705-3709.
  • 6Coffie R. Analytical field plate model for field effect transistors [J]. IEEE Transactions on Electron Devices, 2014, 61(3): 878-883.
  • 7Sun Weifeng, Shi Longxing. Analytical models for the surface potential and electrical field distribution of bulk-silicon RESURF devices [J]. Solid-State Electronics, 2004, 48(5): 799-805.
  • 8Chung S K, Han S Y. Analytical model for the surface field distribution of SOI RESURF devices [J]. IEEE Transactions on Electron Devices, 1998, 45(6): 1374-1376.
  • 9Huang Haimeng, Wang Yongwei, Chen Xingbi. An analytical model for SOI triple RESURF devices [C]//IEEE 9th International Conference on ASIC. Xiamen, China, 2011: 547-550.
  • 10李琦,张波,李肇基.带p埋层表面注入硅基LDMOS模型与优化[J].Journal of Semiconductors,2007,28(8):1267-1271. 被引量:4

二级参考文献40

  • 1孙智林,孙伟锋,易扬波,陆生礼.高可靠性P-LDMOS研究[J].Journal of Semiconductors,2004,25(12):1690-1694. 被引量:6
  • 2李琦,张波,李肇基.阶梯掺杂薄漂移区RESURF LDMOS耐压模型[J].Journal of Semiconductors,2005,26(11):2159-2163. 被引量:3
  • 3Sun Weifeng, Wu Jianhui, Yi Yangbo, et al. High- voltage power integrated circuit technology using bulk- silicon for plasma display panels data driver IC[ J]. Mi- croelectron Eng,2004, 71(1) : 112 - 118.
  • 4Kim J, Roh T M, Kimet S G, et al. High-voltage pow- er integrated circuit technology using SOI for driving plasma display panels [J]. IEEE Trans Electron De- vices, 2001, 48(6) : 1256 - 1259.
  • 5Sun Weifeng, Wu Hong, Shi Longxing, et al. On-re- sistance degradations for different stress conditions in high-voltage pLEDMOS transistor with thick gate oxide [J]. IEEE Electron Device Letters, 2007, 28 (7) : 631 - 633.
  • 6Lee S K, Kim C J, Kim J H, et al. Optimization of safe-operating-area using two peaks of body-current in submicron LDMOS transistors [ C ]//Proceedings of ISPSD. Osaka, Japan, 2001:287 -290.
  • 7Huang D H, King E E, Palkut L J. Characterization of hot-carrier-induced degradation in p-channel MOSFET's by total injected charge techniques[C ]//IEEE Reliabili- ty Physics Symposium. San Jose, CA, USA, 1994:31 -41.
  • 8Chen J F, Tian K S, Chen S Y, et al. On-resistance degradation induced by hot-carrier injection in ldmos transistors with STI in the drift region [ J ]. IEEE Elec- tron Device Letters, 2008, 29(9) : 1071 - 1073.
  • 9Chen J F, Tian K S, Chen S Y, et al. An investigation on anomalous hot-cartier-induced on-resistance reduction in n-type ldmos transistors [ J ]. IEEE Trans on Device and Materials Reliability, 2009, 9 ( 3 ) : 459 - 463.
  • 10Goud C B, Bhat K N. Two-dimensional analysis and design considerations of high-voltage planar junctions equipped with field plate and guard ring [ J ].IEEE Trans Electron Devices,1991, 38(6) : 1497 -1504.

共引文献7

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部