6-T CMOS SRAM单元稳定性分析及设计优化

Stability Analysis and Design Optimization of 6-T CMOS SRAM Cells

介绍了一种由两个交叉耦合反向器构成的6-晶体管(6-T)存储单元的噪声容限分析方法。对6-T CMOS SRAM单元的稳定性作了分析及仿真。借助SPICE和MATLAB工具,对存储单元在数据保持和数据读取时的稳定性、数据写入过程中的可靠性及其之间的关系进行了深入研究。对可能影响噪声容限的因素,如单元比、上拉比、MOS管的阈值电压、位线预充电压、电源电压以及温度进行了仿真讨论,并从中得到合适的电路设计参数。流片结果表明,理论分析与实测数据相符。分析数据对基于CSMC 0.5μm CMOS工艺的SRAM电路设计优化具有指导作用。

A method for characterizing the noise margin of a 6-Tansistor（ 6-T） memory cell formed by two cross-coupled inverters was introduced. The stability of 6-T CMOS SRAM cells was investigated and simulated. By using the SPICE and MATLAB software,the cell stability during data hold and read period as well as its relationship with write ability were deeply investigated. The effects of several parameters which may have impact on the noise margin such as cell ratio, pull-up ratio, MOS threshold voltage,bit-line pre-charge voltage, power supply voltage and temperature were simulated and discussed. The design parameters for the circuit were obtained. The test results show that theoretical analyses agree with the measured data. The statistical results have a guidance function to SRAM circuit design optimization based on 0. 5 μm CSMC CMOS process.