基于仲裁器PUF的SRAM FPGA防克隆技术设计与实现

Design and Implementation of Anti-Cloning Technology for SRAM FPGA Based on Arbiter PUF

为保护电子设备中使用的静态随机存储器(SRAM)型现场可编程门阵列(FPGA)内部电路设计不被窃取,设计了用于SRAM FPGA的防克隆电路。该电路利用FPGA制造过程中的随机误差,提取每块芯片独一无二的ID。在此ID的控制下,被保护电路只能在指定的FPGA中正常运行,而在未指定的FPGA中运行时,无法产生正确的输出,从而达到防克隆目的。防克隆电路由使用仲裁器的物理不可克隆函数(PUF)、多数表决器、运算门阵列等三部分构成,其中仲裁器PUF电路用于提取ID,多数表决器起到提高输出稳定性的作用。最后在FPGA开发平台上证明了该电路的可行性。

Against the cloning of internal circuit design of static random access memory field programmable gate array（ SRAM FPGA） used in the electronic equipment,an anti-cloning circuit was designed for SRAM FPGA. Random errors during FPGA manufacture process were used to extract unique ID for each FPGA. Under the control of the ID,the protected circuit can only perform correctly in appointed FPGA,and it can＇t output correctly when performing in unspecified FPGA to prevent the anticloning. The anti-cloning circuit was composed of arbiter physical unclonable function（ PUF）,majority voter and operation gate array. Arbiter PUF is used to extract unique ID and majority voter is applied to promote the output stability. Finally,the design was implemented on FPGA platform. The result shows that the anti-cloning circuit can perform well.