640×512焦平面读出电路设计

640×512 Focal Plane Array Readout Circuit Design

介绍了640×512电容反馈跨阻放大器(CTIA)型焦平面读出电路的设计,包含模拟电路与数字模块设计。分析了CTIA采样单元的设计,折中优化了采样单元的面积、噪声、增益等因素,同时优化了采样单元控制电路,最大限度地提高了对采样单元阵列的驱动能力;数字控制部分着重分析了对行选、列选、翻转读出、随机开窗、隔行扫描、多路选择输出等功能的实现方式。设计基于0.5μm DPTM工艺进行仿真验证,采样单元面积为25μm×25μm,工作频率为5MHz,芯片面积为18.1mm×17.4mm,输出摆幅大于2.5V,动态范围大于70dB。

Introduced is the design of focal plane array readout circuit, including the analog circuit and the digital circuit, for 640 × 512 capacitor feedback transimpedance amplifier （CTIA）. For the analog circuit, it is focused on the design of CTIA sampling cell and the factors such as its area, noise and gain are optimized, and meanwhile the cell control circuit is optimized so as to realize a higher driving current. For the digital control circuit, it is focused on the implementations of such functions as line select, column select, flip read, random windows, interlaced scanning and selectable number of outputs. Verifications were performed based on 0.5 μm DPTM process, the parameters as the cell area of 25μm× 25μm, the operating frequency of 5MHz, the die size of 18. 1 min×17.4 mm, the output swing of larger than 2.5 V, and the dynamic rang of beyond 70 dB are realized.