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基于USB 2.0/MAC协议变换的延长系统设计

Design of extended system based on USB 2.0/MAC protocol conversion
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摘要 为克服通用串行总线(USB)在远程通信中的不稳定性和传输时延问题,延长USB接口的传输距离,提出一种修改和自定义的以太网MAC协议,并采用该协议与USB 2.0协议之间的协议转换技术,建立一种基于FPGA的USB延长系统。数据由USB设备/主机传入FPGA中处理,通过USB 2.0接口传至主机/USB设备并作出响应,实现双向数据传输。结合FPGA和Quartus II软件平台完成设计验证,验证结果表明,该延长系统具有良好的可行性、稳定性和兼容性。 To overcome the instability and transmission delay problems of universal serial bus(USB)in communication,and to further extend the transmission distance of USB interface,an FPGA-based extension system was developed by using USB 2.0and a modified and customized Ethernet MAC protocol conversion technology.The whole system and functional modules were designed according to the protocol conversion principle.Data were transmitted from the USB devices/host to the FPGA for processing and then sent back to the host/USB devices via USB 2.0interface and responded.The two-way data transmission was realized.The design verification completed by combining FPGA and Quartus II software platform proves the feasibility,stability and compatibility of the extension system.
出处 《计算机工程与设计》 北大核心 2015年第4期906-910,共5页 Computer Engineering and Design
基金 江苏省自然科学基金项目(BK20130156) 江苏高校优势学科建设工程基金项目(PAPD) 中央高校基本科研业务费专项基金项目(JUSRP1026 JUSRP51323B)
关键词 通用串行总线 以太网 媒体接入控制 现场可编程门阵列 延长系统 USB Ethernet MAC FPGA extension system
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  • 1宋宇鲲,王锐,胡永华,高明伦.使用排队论模型对FIFO深度的研究[J].仪器仪表学报,2006,27(z3):2485-2487. 被引量:10
  • 2刘中,李成贵.交换式以太网在航空电子系统中的应用[J].兵工自动化,2006,25(1):16-17. 被引量:6
  • 3徐阳扬,周端,杨银堂,王青松,廖峰.非对称GALS系统异步接口设计[J].西安电子科技大学学报,2007,34(2):294-297. 被引量:7
  • 4DALLY W J, POULTON J W. Digital systems engineering [M]. Cambridge, UK: Cambridge University. Press, 1998.
  • 5BALCH M. Complete digital design[M]. New York: McGraw-Hill, 2003.
  • 6APPERSON R W. A dual-clock FIFO for the reliable transfer of high-throughput data between unrelated clock domains[D]. California: UC Davis, 2004.
  • 7COCHRAN A J, BAILEY P N, CARR L S. FIFO buffer depth estimation for asynchronous gapped payloads: United States Patent. US, 7227876B 1 [P]. 2007-06-05.
  • 8RHA Kyoungscok, CHOI Kiyoung. Arca-efficient buffer binding based on a novel two-port FIFO structure[C]// Proceedings of the Ninth International Symposium on Hardware/Software Codesign. Copcnhagcm: ACM, 2001: 122-127.
  • 9APPERSON R W, YU Z, MEEUWSEN M J, et al. A scalable dual-clock FIFO for data transfers between arbitrary and haltable clock domains[J]. IEEE Transactions on Very Large Scale Integration (VLS1) Systems, 2007, 15(10): 1125-1134.
  • 10Ahera Corporation. Avalon interface specifications[ EB/OL]. San Jose: Ahera Croporation, 2008 [ 2009-01-10 ]. http://www.altera. com/literature/manual/mnl_avalon spec. pdf.

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