一种高效视频编码插值滤波VLSI架构设计

An Efficient VLSI Architecture Design of High Efficiency Video Coding Interpolation Filtering

最新视频编码标准高效视频编码(HEVC)将8抽头内插值滤波器应用于分数像素运动估计中。相比H.264/AVC标准中使用的6抽头内插值滤波器,虽然提高了精确度,但增大了超大规模集成电路(VLSI)实现的面积。为此,设计一个内插值滤波器VLSI架构。为便于VLSI实现,提出一种快速内插值滤波算法,并在此基础上,构造可重构配置和单元块复用的内插值滤波器VLSI架构,以降低硬件的实现面积。实验结果表明,与未优化的VLSI架构相比,该架构能降低实现面积和提高工作频率,节省大量的存储RAM,可支持4∶2∶0格式的3 840×2 160视频序列的实时处理。

In the latest video compression standard,a new 8-tap Motion Estimation（ ME） interpolation filtering is adopted in High Efficiency Video Coding（ HEVC）. Although the new 8-tap filter can improve the precision compared w ith the 6-tap interpolation filter used in H. 264 / AVC,it also increases the Very Large Scale Integration（ VLSI） efficient area. A high performance VLSI architecture for HEVC interpolation filter is proposed. A fast and hardw areimplementation-friendly interpolation filtering algorithm is presented. Based on the fast algorithm,this paper designs and realizes the interpolation filter VLSI structure of the reconfigurable and the multiplexing of the cell block to reduce the efficient area of hardw are. Experimental results show that,compared w ith the non-optimized VLSI architecture,the proposed VLSI architecture not only reduces the area and improves the w orking frequency,but also saves a lot of RAM.It can support the real-time processing of 4： 2： 0 format 3 840 × 2 160 video sequences.