摘要
码率控制是视频编码中的关键问题,而码率控制实质上是对给定码率要求下的率失真进行优化的问题。为了满足高速场合实时性需求,采用流水线结构,以及运算器时分复用策略,改进了DNx HD编码的码率控制算法,以使其适合在FPGA上实现。实验结果表明,该算法在FPGA上运行稳定,并有较好的码率控制效果。
Rate control is the key problem in video codec. In essence, it is rate distortion optimization under the constraint of a given rate. In order to meet high-speed applications, the DNxHDcodec rate control algorithm was designed and implemented on the platform of Kintex7 Xilinx FPGA. This design takes the advantage of the pipeline structure and time division multiplexing strategy. The experiment result shows that the design gains good control result and runs stable on FPGA.
出处
《电子科技》
2015年第4期46-50,共5页
Electronic Science and Technology
