基于PLB双总线高速存储接口的设计与实现

Design and Implementation of High Speed Memory Interface Based on Dual-PLB-slaves

文中介绍了符合Core Connect规范的高性能处理器局部总线在So C芯片中的应用。为了提高基于PPC架构的So C芯片性能,增加存储带宽利用率,提出一种基于PLB双总线的高速存储接口的设计。文中还描述了高速从接口和DDR3控制器的体系架构设计,并通过对DDR3控制器的数据训练和自测试等关键技术和难点的介绍,实现了高速存储系统的设计。通过仿真可知,基于该接口的So C芯片中DDR3 SDRAM的带宽利用率能提高到85%以上。通过PCB板上信号完整性分析表明,该接口应用于电路板上的走线串扰小,测试得到的眼图清晰端正,满足设计要求。

It introduces the application of PLB bus in the SoC, which follows CoreConnect bus specification. In order to improve the performance of SoC based on PowerPC and increase the storage bandwidth utilization, present an efficient memory interface based on two PLB, also introduce the architecture of high speed slave interface and of DDR3 controller. Through introducing the key techniques and difficult problems of data training and self-test for DDR3 controller,implement the design of high speed memory system. According to simulation result, the bandwidth utilization ratio of this memory interface can reach to 85 %. The signal integrity analysis on PCB has presented that the placement and routing is good and the read data-eye is complete and clear.