HEVC帧内预测Planar和DC模式的VLSI架构设计与实现

Efficient VLSI architecture for Planar and DC mode in HEVC intra prediction

在研究新一代高性能视频编码标准(HEVC)帧内预测中planar和DC模式预测算法的基础上,分别设计了高效VLSI架构,通过状态机的自适应控制和模块的复用来实现速度的提高和面积的减少。针对planar模式,设计了一种基于状态机自适应控制的寄存器累加架构;针对DC模式,设计了一种基于算法的分割处理架构。实验结果表明,所设计的架构在TSMC180 nm的工艺下最高频率为350 MHz,面积合计为68.1 kgate,能够实现对4∶2∶0格式7 680×4 320@30 f/s视频序列的实时编码,最高工作频率可以达到23.4 MHz。

Efficient intra prediction VLSI architecture for HEVC based on the adaptive control of the state machine and the reuse of module is proposed in this paper to realize the increase of the speed and decrease of the area. An accumulation architecture of register is proposed for planar prediction mode and a partition handling architecture is proposed for DC pre-diction mode. The simulation result shows that the proposed VLSI architecture can achieve 350 MHz on TSMC 180 nm, the total area is 68.1 kgate. The speed of the real-time encoding application can achieve 23.4 MHz for SHDTV7680 × 4320@30 f/s.