基于FPGA的高速数字上变频器设计

Design of High-Speed Digital Up-Convertor Based on FPGA

介绍了一种利用FPGA芯片设计高速数字上变频器的方法。该方法采用一种新的多相插值滤波器结构,利用Xilinx FPGA中的硬核资源DSP48,极大地提高了系统的性能;采用一种并行结构的数字控制振荡器,可产生高数据速率的上变频本振信号。与传统方案相比,利用该方法设计的数字上变频器具有更好的性能和更大的实现灵活性,其输出数字中频信号的数据率可达1GS/s。另外,利用FPGA芯片的可编程性,可根据需要下载不同的程序代码,以满足不同通信功能的要求。

A new method to realize high speed digital up converter（DUC）was presented by using FPGA.This method adopted a novel implementation structure of polyphase interpolation filter and made use of the DSP48 hard cores in Xilinx FPGA to improve the system＇s performance.Besides,the adoption of parallel structure numerically controlled oscillator（NCO）could generate high data rate vibration signal.Compared with traditional methods,the DUC designed with this method had higher performance and better flexibility,which could generate digital IF signals with data rate up to 1GS/s.In addition,through the programmable FPGA chips,different program codes could be downloaded as needed to meet the requirements of different communication functions.