一种0.2mm^2 10位50MS/s流水线型模数转换器

A 0.2 mm^2 10 Bit 50 MS/s Pipelined ADC

设计了一款适用于无线通讯系统的3.3V,10位50 MS/s流水线型模数转换器。减小面积和功耗是设计的核心。通过运放共享技术,减小了芯片功耗和面积;使用耗尽型MOS管改进的CMOS开关替代栅压自举开关,节省了开关面积;采用薄栅器件作为主运放的输入管,提高了运放带宽,减小了运放的面积和功耗;采用耗尽型MOS管设计辅助运放,减小了辅助运放的功耗。基于华虹NEC 0.13μm 1P6M CMOS工艺,ADC核心版图面积仅为0.2mm2,功耗为45mW;在50 MHz采样频率,11 MHz输入信号下,SFDR达78dB,SNDR达60.7dB,有效位数为9.8位。

A 3.3V10 bit 50MS/s pipelined ADC for wireless communication was proposed.It is critical for the design to reduce the area and power consumption.By employing op-amp sharing technique,an optimized CMOS switch using depletion mode NMOS devices replaced the gated boost switch,which reduced the switch＇s area.Thin oxide devices were used as the main op amp＇s input,which increased the op-amp＇s bandwidth and reduced the opamp＇s area and power consumption.Depletion mode NMOS devices were used for the auxiliary op-amp to reduce the power consumption.Implemented in HHNEC 0.13μm 1P6 M CMOS process,the proposed ADC only occupied a core area of 0.2mm2 and dissipated 45 mW from 3.3Vsupply.The circuit achieved an SFDR of 78 dB,an SNDR of 60.7dB at an input frequency of 11 MHz and an ENOB of 9.8bit when the sampling frequency was 50 MHz.