一种用于低功耗TDC系统基于D触发器链的TDC使能电路

A TDC Enabler Based on DFF Chain for Low Power TDC System

时间数字转换器(Time-to-Digital Converter,TDC)是全数字锁相环(All-Digital PhaseLocked Loop,ADPLL)中的一个重要模块,其功耗也是ADPLL系统总功耗的主要部分。针对伪差分反相器链结构的TDC,提出了一种功能不受亚稳态影响的基于D触发器链的TDC使能电路,并对TDC的结构进行改进,以降低TDC系统的功耗。采用SMIC 0.18μm CMOS工艺对电路进行设计和仿真,仿真结果表明,TDC系统的功耗可以降低74%以上。

Time-to-digital converter（TDC）was a key block in an all-digital phase-locked loop（ADPLL）,with its power consumption being one of the major parts of the power consumption of the whole ADPLL system.A TDC enabler based on DFF chain whose function would not be affected by metastability was proposed for the TDC based on two pseudo-differential inverter-delay chains.Some modifications to the architecture of the TDC were done to reduce the power consumption of the TDC system.The circuit was designed and simulated in the SMIC 0.18μm CMOS process.The simulation results showed that the power consumption of the TDC system could be reduced by more than 74%.