面向高精度互连时延分析的电路网表生成方法

A Generation Method for the High-precision Interconnect Delay Analysis of Circuit Netlist

面向高精度时延分析,提出基于场求解器电容提取的自动互连电路网表生成方法。通过分析三维互连结构数据,实现互连线网中导体块之间连接关系判断;然后用图的广度优先遍历算法重新排序导体块,最后结合电阻电容提取结构生成SPEF和SPICE两种电路网表。基于实际互连结构的实验验证了该方法的正确性和有效性。

For high-precision delay analysis,a netlist generation method of automatically interconnect circuit based on field solver capacitance extraction is proposed.Firstly,the connection relationship between conductors in the interconnection network can be checked according to analyses of the three-dimensional interconnect structure data.Then the figure breadth-first calendar calculation method to reorder again conductor block is used.Finally,resistance and capacitance extraction structure is combined to generate SPEF and SPICE two kinds of the circuit netlist.The actual interconnection structure of the experiment shows the correctness and validity of the method.