基于FPGA的LDPC编码器设计

Design of LDPC Encoder Based on FPGA

本文介绍了一种在FPGA上实现，利用有效校验矩阵来降低编码复杂度的LD-Pc编码方案，给出了编码器设计实现的算法和编码器基本组成。并在Quartus119．1软件平台上采用基于FPGA的VHDL语言实现了有效的编码过程。

This paper presents a LDPC encoding scheme suitable for FPGA by using effective check matrix to reduce the complexity of the encoding. It gives the design and algorithm of the encoder as well as its basic components. The effective encoding process based on FPGA with VHDL language is implemented on QuartusII9. 1 software platform.