异步流水线架构Mousetrap的教学实践

Teaching Practical of Asynchronous Pipelined Architecture Mousetrap

本文以数据包异步流水线架构Mousetrap的设计为例,介绍了利用LT Spice进行异步电路设计的思路及方法。设计采用0.18μm CMOS工艺,利用Mousetrap流水线单元设计1比特-四级异步1×4 FIFO电路。将其分解为两个核心模块:锁存器模块和Mousetrap流水线控制模块。这表明利用LT Spice实现数据包异步流水线架构Mousetrap的方法和步骤,通过软件进行功能仿真,验证设计的正确性。

This paper takes the example of bundled data asynchronous pipelined architecture Mousetrap to illustrate the design method of asynchronous circuits based on LT Spice. An 0. 18-μm CMOS technology is used,and 1 bit-4 level asynchronous FIFO circuit based on Mousetrap pipeline is designed. The design is divided to two main mod-ules：latch and bundled data asynchronous pipelined Mousetrap control module. The method and steps to realize the bundled data asynchronous pipelined architecture Mousetrap is explained,functional simulation is performed to prove the correctness of the design.