基于延迟锁定环技术的数字脉宽调制器的设计与实现

The Design and Implementation of a Delay Lock Loop Digital Pulse Width Modulator

介绍了一种新型的基于数字延迟锁定环DLL(Delay Lock Loop)技术的混合数字脉宽调制器DPWM(Digital Pulse Width Modulator)结构,该结构用可编程延迟单元PDU(Programmable Delay Unit)构成延迟线,通过DLL调节算法,动态地调整PDU的延迟时间,从而消除了延迟线的延迟时间受工艺、温度、工作电压的影响,提高了PWM的调节线性度,适用于数字控制开关式电源SMPS(Switched-Mode Power Supply),可以大幅度的提升系统的性能。同时,此种结构的DPWM适合FPGA验证和流片实现。采用CMOS 0.18μm工艺对所提出的结构进行了设计与实现,DPWM占用面积0.045 7 mm2,芯片测试结果非常好,可以进行工程应用。

A novel digital pulse width modulator（ DPWM） architecture that based on DLL technology is introduced,which applies to switched-mode power supply（ SMPS）. The delay line of this DPWM take advantage of the programmable delay unit（ PDU） and the DLL technology to eliminate the influence of process,temperature and voltage,which improve the linearity of PWM dramatically. This DPWM is well suited for FPGA or custom chip implementation. The IC occupying only 0. 045 7mm2 silicon area is implemented in a CMOS 0. 18μm process,the measure results meet with the demand and the DPWM can fit the engineering application.