一种滞回比较器设计

Design of a Hysteresis Comparator

比较器广泛应用于模拟信号到数字信号的转换过程中,在模-数转换过程中,对输入进行采样后的信号通过比较器以决定模拟信号的数字量。滞回比较器也叫迟滞比较器,以其优越的抗噪声能力在比较器中占有重要地位。描述一种滞回比较器,使用少量元件节省成本,滞回电压阈值设计灵活,同时用P管作差分输入管,有较高的共模输入范围,转换速率快。使用0.18μm CMOS工艺分别对转折点压差为200 m V的设计进行仿真,仿真结果与设计预期相符合。

Comparator is widely used in conversion of analog signal to digital signal. In analog-to-digital conversion, the input signal is sampled by comparator to determined the output digital signal. Hysteresis comparator also called sluggish comparator with superior anti noise ability plays an important role in comparator. The paper describes a hysteresis comparator with simple structure and hysteresis voltage threshold design flexibility. At the same time PMOS are the differential input transistors and the comparator has high common mode input range and large slew rate. The design with turning point of voltage difference 200 m V is simulated with 0.18 μm CMOS process and the results are accord with the desired outcome.