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刍议集成电路老化预测与容忍

Aging Prediction and Tolerance of Integrated Circuit
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摘要 集成电路特有的制备工艺,正在不断拓展。电源电压被限缩,提升了原有的集成性能。这种情形下,集成电路关涉的多重产业,也在快速进展。然而,伴随性能渐渐完善,集成电路潜藏着的老化疑难,也在逐渐凸显。拟定好的特征尺寸缩减,各时段的负偏置温度,凸显了不稳定的总倾向[1]。为此,有必要明晰老化预测特有的多重属性,探究可用的容忍技术。 Integrated circuit production technology is continuously developing. The power supply voltage is reduced and the integrated circuit performance becomes better. However,with the perfect performance of integrated circuit,the aging problems of it are increasing. The feature size reduction of integrated circuit and the negative bias temperature instability in each period highlights a instable general tendency. Therefore,the aging prediction technology should be analyzed and the aging tolerance technology should be explored.
作者 贾利芳
出处 《山西电子技术》 2015年第2期19-20,共2页 Shanxi Electronic Technology
关键词 集成电路 老化预测 容忍老化 integrated circuit aging prediction aging tolerance
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  • 1李忠贺,刘红侠,郝跃.超深亚微米PMOS器件的NBTI退化机理[J].物理学报,2006,55(2):820-824. 被引量:8
  • 2W Jinhui, W Wuchen, G Na,H Ligang. Domino gate with modified voltage keeper [A]. Proceedings of Quality Electronic Design (ISQED), 2010 llth International Symposium on [C]. 2010.443-446.
  • 3V Kursun, E G Friedman. Domino logic with variable threshold voltage keeper [J]. Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, 2003, 11(6): 1080-1093.
  • 4S A Tawfik, V Kursun. FinFET domino logic with independent gate keepers [J]. Microeleetronies Journal, 2009, 40(11): 1531-1540.
  • 5W Wenping, Y Shengqi, S Bhardwaj, R Vattikonda, S Vrudhula, F Liu, C Yu. The Impact of NBTI on the Performance of Combinational and Sequential Circuits [A]. Proceedings of Design Automation Conference [C]. 2007. DAC '07.44th ACM/IEEE, 2007. 364-369.
  • 6S Kothawade, K Chakraborty, S Roy. Analysis and mitigation of NBTI aging in register file: An end-to-end approach [A]. Proceedings of Quality Electronic Design (ISQED), 2011 12th International Symposium on [C]. 2011. 1-7.
  • 7M Agarwal, V Balakrishnan, A Bhuyan, K Kyunglok, B C Paul, W Wenping,'Y"B'o, C Yu, S Mitra. Optimized Circuit Failure Prediction for Aging: Practicality and Promise [A]. Proceedings of Test Conference, 2,00~.ITC 2008. IEEE International [C]. 2008. 1-10.
  • 8M Agarwal, B C Paul, Z Ming ,S Mitra. Circuit Failure Prediction and Its Application to Transistor Aging [A]. Proceedings of VLSI Test Symposium, 2007.25th IEEE [C]. 2007. 277-286.
  • 9R S Oliveira, J Semiao, I C Teixeira, M B Santos, J P Teixeira. On-line BIST for performance failure prediction under aging effects in automotive safety-critical applications [A]. Proceedings of Test Workshop (LATW), 2011 12th Latin American [C]. 2011. 1-6.
  • 10C V Martins, J Semiao, J C Vazquez, V Champac, M Santos, I C Teixeira, J P Teixeira. Adaptive Error-Prediction Flip-flop for performance failure prediction with aging sensors [A]. Proceedings of VLSI Test Symposium (VTS), 2011 IEEE 29th [C]. 20ll. 203-208.

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