基于深亚微米工艺长互连线延迟优化的设计方法研究

Interconnect Delay Optimization for Deep Submicron Technology

随着SoC方法学的使用,集成电路越来越复杂,设计规模越来越大,连线延时已经成为影响时序收敛的关健因素之一.本文提出了一种基于物理设计的长线互连优化方法,即优化关键单元的布局,并选取、增、减repeater来优化时序.本方法根据单元间的位置测定单元间距,指导设计中需要插入的repeater位置及数量.长互连延迟的优化效果与所使用的单元、插入单元的间距、选用的线宽等影响因素有密切关系.28nm工艺下,在间距200μm^250μm时插入8倍驱动(×8)规格的反相器(缓冲器)时效果最好.其次,将互连线上的缓冲器换成反相器,互连延迟能降低10%.第三,使用更宽的走线能使长互连线延时再降低20~30ps.

As manufacturing technology for Integrated Circuit （IC） enters into 28nm technology node, the number of transistors on chip keeps on growing dramatically all the time, and interconnect delay has become one of the major obstacles of timing closure for IC designs. This paper proposed a physical-aware long-interconnect optimization methodology. The main idea of the proposed methodology is that. key cells/elements for long-interconnect delay optimization are identified and placed at place stage in EDA tools; And then,timing delay is optimized by adding/deleting buffer cells. The proposed methodology pro- vides a solution to the problem of long-interconnect optimization issue for VLSI design in EDA tools. Ex- perimental results indicate that：1） the quantity of buffers to be inserted can be guided by the interconnect distance between the key elements and optimized according to the specific design requirements, and using × 8 buffer between the distance in 200μm and 250μm can obtain the most effective effecti2） substituting the buffers with inverter-pairs can reduce the total interconnect delay dramatically by 10%; 3） using wide met- al can further reduce interconnect delay for 20~30 ps.