一种多级运动估值VLSI结构的设计

A VLSI Architecture of a Hierarchical Motion Estimator

提出了一种新的多级运动估值器的结构 ,它支持低比特视频编码器的高级预测模式 ,如H.2 63和 MPEG- 4。该 VLSI结构的所有级别中共用一个基本的搜索单元 ( BSU) ,减小了芯片尺寸。另外 ,由于它为计算 8× 8块的绝对误差和 SAD提供了一种对存储器数据流的控制电路 ,因此 ,对于高级预测模式 ,可同时获得 1个宏块运动矢量和每个宏块中的 4个子块运动矢量。这种尺寸较小的运动估值电路可以获得与全搜索块匹配算法 ( FSBMA)

A new architecture of hierarchical motion estimator is presented, which supports the advanced prediction mode of recent low bit rate video coders such as H 263 and MPEG 4 In the proposed VLSI architecture, a basic searching unit (BSU) is commonly utilized for all hierarchical levels to make a systematic and small sized motion estimator Also, since the memory bank of the proposed architecture provides a scheduled data flow for calculating the 8×8 block based sum of absolute difference (SAD), both a macroblock based motion vector (MV) and four block based MVs per macroblock can be simultaneously obtained for the advanced prediction mode Small as it is, the proposed motion estimator provides coding performance similar to that for the full search block matching algorithm (FSBMA)