浮点加法器的低功耗结构设计

Design of a Low Power Architecture for Floating-Point Adders

浮点加法器是集成电路数据通道中重要的单元 ,它的性能和功耗极大地影响着处理器和数字信号处理器的性能。文章分析了浮点加法器的几种结构 ,重点介绍了实现低功耗的三数据通道结构。最后 。

Floating point adder is an important block in IC datapaths Its performance and power consumptions have a great effect on the performance of processors and DSP's In this paper, several architectures for floating point adder are summarized and analyzed A low power triple datapath architecture is described in particular Finally, the practicability of floating point adder architecture has been analyzed