用于环路校准的延迟锁相环设计

Design of delay-locked loop for loop calibration

延迟锁相环能够产生精确的延时而被广泛使用。本文介绍了一种适用于直接调制发射机锁相电路环路校准的延迟锁相环。电路采用TSMC 0.18μm CMOS工艺实现,参考频率为26 MHz。在3.3 V电源电压下的仿真结果显示:延迟锁相环锁定时间为520ns,锁定相位为2π,同时输出8路相位差为45o间隔的时钟。

Delay locked loop is widely used because it may generate an accurate delay. This paper introduces a delay locked loop applied to loop calibration for PLL circuit of direct modulation transmitter. The whole circuit used TSMC 0.18μm CMOS technology with a reference frequency of 26 MHz. The power supply is 3.3V. The simulation results show that the circuit has a locking time of about 520ns and a locking phase of 2π. It also can output eight clocks with the same phase interval of 45o.