摘要
通过对锁相环（PLL）与直接数字频率合成器（DDS）的工作原理分析,得出PLL相位噪声数学模型与减小DDS杂散的方法。介绍了一种S波段的宽带小步进频率合成器的设计与实现,并通过了实物制作与测试。测试在输出频率范围为1 800~2 350 MHz、频率步进为10 k Hz时,相位噪声为-88 d Bc/Hz@10 k Hz,杂散低于-60 d Bc。测试结果证明,该频率合成器的性能达到了设计指标要求。
By analyzing the theory of phase-locked loop （PLL） and direct digital synthesizer （DDS） ,the working model of phase lock loop noise and the method of lowering the spurious frequency of DDS are obtained.A design and implementation of S-band frequen- cy synthesizer with broadband and fine resolution are introduced, which is produced and tested. Meanwhile, a design of 1 800 - 2 350 MHz frequency synthesizer with 10 kHz step is realized.Through hardware test,the phase noise is -88 dBc/Hz@ 10 kHz and the spurious frequency is less than -60 dBe.The test results show that this frequency synthesizer can meet the design requirements.
出处
《无线电工程》
2015年第5期70-72,共3页
Radio Engineering
基金
国家部发基金资助项目
关键词
DDS
锁相环
相位噪声
杂散
DDS
phase-locked loop
phase noise
spurious frequency
