期刊文献+
任意字段
题名或关键词
题名
关键词
文摘
作者
第一作者
机构
刊名
分类号
参考文献
作者简介
基金资助
栏目信息

一种多协议统一架构CMOS Serdes发送器电路设计 被引量：2

Design of a Multi Protocol Unified Architecture CMOS Serdes Transmitter Circuit
下载PDF
导出
摘要 为了满足SoC系统对多种高速串行通信协议的兼容性要求,文中提出了一种最高支持3.125 Gbps的多协议统一架构Serdes发送器电路结构,并在0.13μm CMOS工艺下实现。该结构通过分频比可编程的PLL电路来产生不同频率的时钟信号,并通过差分电荷泵电路降低了的分频比可调地降低了PLL电路输出时钟信号的抖动;通过上升/下降时间控制电路来改变输出信号的上升/下降沿时间,并通过控制信号来改变驱动器的输出信号幅度以及预加重幅度,从而满足不同协议对输出信号的上升/下降时间以及输出幅度的要求。测试结果表明,该发送器电路输出信号眼图可以满足PCI-E、Fiber Channel、SRIO等协议的模板要求,在3.125 Gbps速率下,其随机抖动RJRMS为1.81 ps。 In order to meet the compatibility requirements of SoC system for a variety of high speed serial communication protocol,pro-pose a multi protocol unified Serdes transmitter architecture which can support maximum 3. 125 Gbps and has been realized in a 0. 13 μm CMOS technology. The dividing ratio of PLL can be programmed to produce different frequency,and the jitter of the PLL output clock is reduced through differential charge pump circuit. This transmitter architecture uses rising/falling edge control circuit to change the rise/fall time of the output signal,and uses control signal to change the amplitude and pre-emphasis amplitude of the driver so as to meet the different protocols requirements. Measurement results show that the output of the transmitter can meet the eye diagram template of the PCI-E,Fiber Channel and SRIO,the random jitter of the transmitter is 1. 81 ps at the rate of 3. 125 Gbps.
作者 唐龙飞 田泽 邵刚
机构地区 中国航空计算技术研究所
出处 《计算机技术与发展》 2015年第5期131-134,共4页 Computer Technology and Development
基金 "十二五"微电子预研(51308010601 51308010711) 总装预研基金(9140A08010712HK6101)
关键词 SERDES 发送器 低抖动 PLL Serdes transmitter low jitter PLL
分类号 TP31 [自动化与计算机技术—计算机软件与理论]
  • 相关文献

参考文献12

  • 1陈钰,洪志良.用于2.5Gbps千兆以太网发接器的时钟倍频器设计[J].固体电子学研究与进展,2003,23(3):256-261. 被引量：5
  • 2PCI express base specification revision 2.0 [ S ]. New York : PCI-SIG Company,2006.
  • 3PCI express card electromechanical specification revision 2.0 [ S]. New York:PCI-SIG Company,2007.
  • 4Stauffer D R, Mechler J T, Sona M, et al. High speed Serdes devices and applications[ M]. [ s. l, ] :Springer Science Busi- ness Media,2009.
  • 5Yokoyama-Martin D A, Krishna K, Stonick J, et al. A multi- standard low power 1. 5 -3. 125Gb/s serial transceiver in 90nm MOS[ C l//Proceedings of IEEE custom integrated cir- cuits conference. [ s. 1. ] :IEEE ,2006:401-404.
  • 6Partovi H ,Evans B ,Wilson T,et al. A 62.5Gb/s multi-stand- ard SerDes IC [ C ]//Proceedings of IEEE custom integrated circuits conference. [ s. 1. ] :IEEE ,2003:585-588.
  • 7Williams S,Thompson H, Hufford M, et al. An improved CM- OS ring oscillator PLL with less than 4ps accumulated jitter [ C]//Proceedings of IEEE custom integrated circuits confer- ence. [s. 1. ] :IEEE,2004:151-154.
  • 8姜梅,刘三清,李乃平,陈钊.用于电荷泵锁相环的无源滤波器的设计[J].微电子学,2003,33(4):339-343. 被引量：11
  • 9Loke A L, Barnes R K, Wee T T, et al. A versatile 90- nm CMOS charge-pupm PLL for SerDes transmitter clocking[ J]. IEEE Journal of Solid- state Circuits, 2006,41 ( 8 ) : 1894 - 1907.
  • 10陈一辉,郭淦,叶菁华,黄林,陈学峰,洪志良.一种采用常跨导偏置技术的高速多相时钟发生器[J].微电子学,2004,34(3):345-348. 被引量：4

二级参考文献30

  • 1[1]Craninckx Jan,Steyaert Michel S J.A 1.8 GHz CMOS low-phase-noise voltage-contralled oscillator with prescaler.IEEE J Solid-State Circuits,1995;SC-30(12):1 474～1 482
  • 2[2]Parker James F,Ray Daniel.A 1.6 GHz CMOS PLL with on-chip loop filter.IEEE J Solid-State Circuits,1998;SC-33(3):337～343
  • 3[3]Park Chan Hong,Kim Beomsup.A low-noise,900 MHz VCO in 0.6 μm CMOS.IEEE J Solid-State Circuits,1999;SC-34(5):586～591
  • 4[4]Kim B,Gray P R.Phase noise analysis for ring oscillator VCO's to be submitted for publication
  • 5[5]Yang Ching Yuan,Dehng Guang Kaai,Hsu June Ming,et al.New dynamic flip-flops for high-speed dual-modulus prescaler.IEEE J Solid-State Circuits,1998;SC-33(10):1 568～1 571
  • 6Franazek P A, Widmer A X. Byte oriented DC balanced (0, 4) 8B/10B partitioned block transmissioncode [P]. U S Patent: 4 486 739, 1984.
  • 7Lee K, Kim S, Shin Y, et al. A jitter-tolerant 4.5Gb/s CMOS interconnect for digital display [A]. ISSCC Digest of Technical Papers [C]. San Francisco..IEEE Press,1998. 302-303.
  • 8Gu R, Tran J M. Lin H-C, et al. A 0.5-3. SGb/s low-power low-jitter serial data CMOS transceiver[A]. ISSCC Digest of Technical Papers [C]. San Francisco: IEEE Press, 1999. 352-353.
  • 9Ewen J F, Widmer A X, Soyuer M, et al. Single-chip 1062M baud CMOS transceiver for serial data communication [A]. ISSCC Digest of Technical Papers [C].San Francisco: IEEE Press, 1995. 32-33.
  • 10Chen D-L, Baker M O. A 1.25 Gb/s, 460mW CMOS transceiver for serial data communication [A]. ISSCC Digest of Technical Papers [C]. San Francisco: IEEE Press, 1997. 242-243.

共引文献23

同被引文献10

引证文献2

二级引证文献2

计算机技术与发展
2015年 第5期

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部