摘要
针对传统的数字信号源存在码速率单一不灵活可调的缺点,设计了基于FPGA的码速率连续可调PCM数字信号源。该设计采用数字频率合成技术DDS,提供频率连续可调的时钟信号,使输出数字信号码速率在1bps^10Mbps连续可调,可实现速度快,步进小,频率分辨率高的调控。实验表明,该信号源可实现输出PCM数字信号,输出信号的码速率可以由用户根据实际需求利用上位机软件设定。
This paper addresses that the code rate of the traditional digital source is single and not flexible adjustable, and designs a PCM digital source with continuously adjustable code rate based on FPGA. The method uses the tech- nology of digital frequency synthesis DDS to provide the clock signal with continuously adjustable frequency making the code rate of signals can be adjust between lbps ~ lOMbps, which can realize regulation and control with characteristics of high speed, small step and high frequency resolution. Experimental results show that the signal source could output PCM digital signals, and the code rate of signals can be set though the upper computer software by the users on the basis of actual demand.
出处
《电测与仪表》
北大核心
2015年第8期91-95,共5页
Electrical Measurement & Instrumentation
基金
国家自然科学基金资助项目(51075375)
关键词
FPGA
数字频率合成
连续可调
信号源
FPGA, digital frequency synthesis, continuously adjustable, signal source
