摘要
This paper describes a 12-bit 125-MS/spipelinedanalog-to-digitalconverter（ADC）thatisimplemented in a 0.18 #m CMOS process. A gate-bootstrapping switch is used as the bottom-sampling switch in the first stage to enhance the sampling linearity. The measured differential and integral nonlinearities of the prototype are less than 0.79 least significant bit （LSB） and 0.86 LSB, respectively, at the full sampling rate. The ADC exhibits an effective number of bits （ENOB） of more than 11.05 bits at the input frequency of 10.5 MHz. The ADC also achieves a 10.5 bits ENOB with the Nyquist input frequency at the full sample rate. In addition, the ADC consumes 62 mW from a 1.9 V power supply and occupies 1.17 mm2, which includes an on-chip reference buffer. The figure-of-merit of this ADC is 0.23 p J/step.
This paper describes a 12-bit 125-MS/spipelinedanalog-to-digitalconverter（ADC）thatisimplemented in a 0.18 #m CMOS process. A gate-bootstrapping switch is used as the bottom-sampling switch in the first stage to enhance the sampling linearity. The measured differential and integral nonlinearities of the prototype are less than 0.79 least significant bit （LSB） and 0.86 LSB, respectively, at the full sampling rate. The ADC exhibits an effective number of bits （ENOB） of more than 11.05 bits at the input frequency of 10.5 MHz. The ADC also achieves a 10.5 bits ENOB with the Nyquist input frequency at the full sample rate. In addition, the ADC consumes 62 mW from a 1.9 V power supply and occupies 1.17 mm2, which includes an on-chip reference buffer. The figure-of-merit of this ADC is 0.23 p J/step.
基金
Project supported by the Foundation of Shanghai Municipal Commission of Economy and Informatization(No.130311)
