摘要
Parallel acceleration of convolution perfectly matched layer （CPML） algorithm suffers from massive division operation which is widely accepted as one of the most expensive operations for the equipment such as graphic processing unit （GPU）, field programmable gate array （FPGA） etc. In pursuit of higher efficiency and lower power consumption, this article revisited the CPML theory and proposed a new fast division-free parallel CPML structure. By optimally rearranging the CPML inner iteration process, all the division operators can be eliminated and replaced by recalculating the related field updating coefficients offline. Experiments show that the proposed division-free structure can save more than 50% arithmetic instructions and 25% execution time of the traditional parallel CPML structure without any accuracy loss.
Parallel acceleration of convolution perfectly matched layer （CPML） algorithm suffers from massive division operation which is widely accepted as one of the most expensive operations for the equipment such as graphic processing unit （GPU）, field programmable gate array （FPGA） etc. In pursuit of higher efficiency and lower power consumption, this article revisited the CPML theory and proposed a new fast division-free parallel CPML structure. By optimally rearranging the CPML inner iteration process, all the division operators can be eliminated and replaced by recalculating the related field updating coefficients offline. Experiments show that the proposed division-free structure can save more than 50% arithmetic instructions and 25% execution time of the traditional parallel CPML structure without any accuracy loss.
基金
sponsored by the National Natural Science Foundation of China (30870577)
