用于12 bit 250 MS/s流水线ADC的运算放大器设计

Design of the Operation Amplifier for 12 bit 250 MS/s Pipelined ADC

设计了一种应用于12 bit 250 MS/s采样频率的流水线模数转换器(ADC)的运算放大器电路。该电路采用全差分两级结构以达到足够的增益和信号摆幅;采用一种改进的频率米勒补偿方法实现次极点的"外推",减小了第二级支路所需的电流,并达到了更大的单位增益带宽。该电路运用于一种12 bit 250 MS/s流水线ADC的各级余量增益放大器(MDAC),并采用0.18μm 1P5M 1.8 V CMOS工艺实现。测试结果表明,该ADC电路在全速采样条件下对于20 MHz的输入信号得到的信噪比(SNR)为69.92 d B,无杂散动态范围(SFDR)为81.17 d B,整个ADC电路的功耗为320 m W。

An operation amplifier circuit for 12 bit 250 MS/s pipelined analog to the digital converter（ ADC） was designed. The fully differential two stage op-amp architecture was used to achieve high gain and large output swing. A modified Miller compensation technique was used to push the second order pole farther,so that the current consumption for the second stage amplifier was reduced,and a larger unit gain bandwidth was achieved. The op-amp was used in the multiplied digital-to-analog converter（ MDAC） for a 12 bit 250 MS/s pipelined ADC. The 12 bit ADC was implemented in0. 18 μm 1P5 M 1. 8 V CMOS process. The test results show that the ADC achieves the signal noise ratio（ SNR）,of 69. 92 d B and spurious free dynamic range（ SFDR） of 81. 17 d B with 20 MHz input signal at full sampling speed,and the power consumption of the ADC is 320 m W.