LED外延片上芯片静电击穿的测试分析

Analysis on the Electrostatic Piercing Test of the chips on the LED Epitaxial Wafers

利用静电仪和HBM模型研究了GaN基LED外延片上芯片的抗静电性能,并根据pn结势垒电容的特性,对实验结果进行了分析。实验结果表明,缺陷击穿与外延片的工艺有着密切的关系;随着外延片上芯片尺寸的增大,其抗静电能力也随之增强。

The antistatic ability of the chips on the GaN-based LED epitaxial wafers was tested using electrostatic analyzer in HBM model. Then the experimental results were analyzed according to the characteristics of the barrier capacitance. It is shown that the defect piercing has a great relationship with wafer epitaxial process and the antistatic ability can be continuously enhanced with the wafer die size increasing. The results were analyzed the features of barrier capacitance.