一种用于CMOS图像传感器的锁相环设计

A Design of Phase-Locked Loop for CMOS Image Sensor

设计了一种用于CMOS图像传感器时钟产生的电荷泵锁相环（CPPLL）电路。基于0.18μm CMOS工艺,系统采用常规鉴频鉴相器、电流型电荷泵、二阶无源阻抗型低通滤波器、差分环形压控振荡器以及真单相时钟结构分频器与CMOS图像传感器片内集成。系统电路结构简洁实用、功耗低,满足CMOS图像传感器对锁相环低功耗、低噪声、输出频率高及稳定的要求。在输入参考频率为5MHz时,压控振荡器（VOC）输出频率范围为40~217MHz,系统锁定频率为160MHz,锁定时间为16.6μs,功耗为2.5mW,环路带宽为567kHz,相位裕度为57°,相位噪声为-105dBc/Hz@1MHz。

A Charge Pump Phase-Locked Loop（CPPLL）circuit for clock generating of CMOS image sensor was designed.A conventional Phase Frequency Detector（PFD）,a current Charge Pump（CP）,the second-order passive impedance type Low-Pass Filter（LPF）,a differential ring Voltage Controlled Oscillator（VCO）and a true signal phase clock structure Divider（DIV）were used to integrate in the CMOS image sensor chip with using 0.18μm CMOS technology in this system.The system is featured as simple structure and low power,and it satisfies the requirements of phase-locked loop with low-power consumption,low-noise,high stability and high output frequency.The system achieves an output frequency of VCO ranging from 40 MHz to 217 MHz,a system locking frequency of 160 MHz,a locking time of 16.6μs,a power consumption of 2.5mW,a loop bandwidth of 567 kHz,aphase margin of 57°and a phase noise of-105dBc/Hz@1MHz at 5MHz input reference frequency.