90nm CMOS工艺下电压触发的ESD检测电路

Voltage triggered ESD detection circuits in a 90nm CMOS process

提出两种90nm 1VCMOS工艺下电压触发的静电放电检测电路.电压触发的静电检测电路避免了纳米级工艺中的MOS电容栅极漏电问题.该检测电路包含一个反馈回路,提高了检测电路的触发效率,同时增加了反馈关断机制,在芯片工作时检测电路由于某些特殊因素误触发后,仍然可以自行关断,而不会进入闩锁状态.在3V静电放电仿真时,该电路能产生28mA触发电流,以开启箝位器件来泄放静电电荷.在25℃正常电压下工作时,漏电流仅为42(45)nA.仿真结果表明,该检测电路可成功用于纳米级CMOS工艺的集成电路静电保护.

Two voltage triggered electrostatic discharge （ESD） detection circuits are proposed in a 90 nm 1 V CMOS process, which can avoid the gate leakage current issue in the nanometer CMOS process. The proposed circuits include feedback loops to enhance the ESD trigger efficiency, and also add turn-off mechanisms, which can turn off the feedback when they are turned on for some unknown reasons and cannot be latched on. Under 3 V ESD simulation, the circuits can inject 28 mA trigger currents into the clamp device. Under the 25~C normal operating condition the leakage current is 42 nA and 45 nA , respectively. Simulation result shows that the circuits can be successfully used in nanometer CMOS process ESD protection.