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一种应用于全数字锁相环的小数分频器设计

Design of a Fractional-N Frequency Divider for ADPLL Application
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摘要 文章针对宽带全数字锁相环（All-Digital Phase-Locked Loop,ADPLL）架构的频率综合器设计了一种适合的宽分频范围的小数分频器.由于经典的宽分频范围的小数分频器结构在边界处会发生失效,文章在分析其他解决方案的同时,提出了利用可变延时单元进行固定相位校准的解决方法.本设计的可变分频比分频器分频比范围为32-127,输入频率为1.8-3.7GHz,面积为0.46mm×0.24mm.测试结果显示,本设计有效地解决了经典宽分频范围的小数分频器结构在边界处会发生失效的问题. A fractional-N frequency divider covering a wide range is proposed for the ADPLL based frequencysynthesizer. Due to the fact that the conventional fractionabN frequency divider can＇t operate in fractional mode atthe boundary of the divider ratio, the paper analysis the other solutions to this problem and give a new way ofphase error calibration with a delay-variable cell. The divider-ratio-variable divider has a wide range from 32 to 127in the aspect of divider ratio; the input frequency range of the divider covers 1.8 GHz to 3.7 GHz and the divideroccupies an area of 0. 46 mmX0. 24 ram. The measured result shows that the proposed architecture can effectivelysolve the problem of fractional operation failure at the boundary.
作者 赵远新 李巍
机构地区 复旦大学专用集成电路与系统国家重点实验室
出处 《复旦学报（自然科学版）》 CAS CSCD 北大核心 2015年第2期148-155,167,共9页 Journal of Fudan University：Natural Science
基金 国家自然科学基金资助项目(61176029) 国家十二五预研课题资助项目(513***)
关键词 全数字锁相环 小数分频器 可变延时单元 all-digital phase-locked loop fractional-N frequency divider delay-variable cell
分类号 TN772 [电子电信—电路与系统]
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参考文献12

  • 1Staszewski R B, Wallberg J L, Rezeq S, et al. All-digital PLL and transmitter for mobile phone [J]. IEEE J Solid-State Circuits, 2005,40(12) : 2469-2482.
  • 2Vercesi L, Fanori L, de Beraardinis F, et al. A dither-less all digital PLL for cellular transmitters[J]. IEEE J Solid-State Circuits, 2012,47(8) : 1908-1920.
  • 3Tierno J A, Rylyakov A V, Friedman D J. A wide power supply range, wide tuning range, all static CMOS all digital PLL in 65 nm SOI [J]. IEEEJ Solid-State Circuits, 2008,43(1): 42-51.
  • 4Borremans J, Vengattaramane K, Giarmini V, et al. A 86 MHz-12 GHz digital-intensive PLL for software-defined radios, using a 6 fJ/step TDC in 40 nm digital CMOS [J]. IEEE J Solid-State Circuits, 2010,45(10) : 2116-2129.
  • 5Liu W, Li W, Ren P, et al. A PVT tolerant 10 to 500 MHz all-digital phase-locked loop with coupled TDC and DCO[J]. IEEEJ Solid-State Circuits, 2010,45(2): 314-321.
  • 6Jin J, Liu X M, Mo T T, et al. Quantization noise suppression in fractional-N PLLs utilizing glitch-free phase switching multi-modulus frequency divider[J].IEEE Transactions on Circuits and Systems I, 2012,59(5) : 926-937.
  • 7Martynenko D, Fischer G, Klymenko O, et al. A low power programmable frequency divider intended for frequency synthesizer designed in accordance with IEEE 802. 15. 4a standard[C]//IEEE International Conference on Circuits and Systems(ICCAS). ICC Jeju, Korea.. IEEE Press, 2012: 21-26.
  • 8Vaucher C S, FerencicI, Locher M, et al, A family of low-power truly modular programmable dividers in standard 0. 35-μm CMOS Technology [J]. IEEE J Solid-State Circuits, 2000,35(7) : 1039-1045.
  • 9Elkholy A, Elshazly A, Saxena S, et al. A 20-to-1 000 MHz -4-14 ps peak-to-peak jitter reconfigurable multi-output all-digital clock generator using open-loop fractional dividers in 65 nm CMOS[C]// IEEE International Solid-State Circuits Conference Digest of Technical Papers(ISSCC). San Francisco, USA.. IEEE Press, 2014. 272-273.
  • 10Huang D P, Li W, Zhou J, et al. A frequency synthesizer with optimally coupled QVCO and harmonic- rejection SSB mixer for multi-standard wireless receiver[J]. IEEE J Solid-State Circuits, 2011,46 (6) : 1307-1320.
复旦学报（自然科学版）
2015年 第2期

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