VLIW体系结构微处理器功能验证模型

VLIW Architecture Microprocessor Functional Verification Model

为了系统而有效地设计微处理器功能验证激励,针对VLIW体系结构微处理器的结构特征,特别是多操作流水线并行特征,提出了VLIW体系结构微处理器的功能验证模型,基于该模型,针对一个规模为1500kbit等效逻辑门的VLIW体系结构微处理器,完成了功能验证方案的制定和105周期功能验证激励的设计.

When the architecture and organization of microprocessor is becoming more and more complex, the problem about how to verify the microprocessor function is becoming more and more important. In order to design the functional verification stimulus of microprocessor effectively, a functional verification model of VLIW architectural processor is introduced, based on the organization characteristic, especially the parallel pipeline, in the VLIW microprocessor. Based on the verification model, a verification schema and 100,000 cycle of stimulus for a VLIW microprocessor design have been finished, which includes about 1500 Kbit gates.