2Dempster A G, Macledod M D. Use of minimum-adder multiplier blocks in FIR digital filters. IEEE transactions on circuits and system-Ⅱ: Analog and Digital Signal Processing, 1995, 42(9) : 569-577
3Rawski M, Tomaszewicz P, Selvaraj H, et al. Efficient implementation of digital filters with use of advanced synthesis methods targeted FPGA architectures /8^th Euromicro conference on Digital System Design. Porto, Portugal, 2005, 0-7695-2433-8/05
4Chapman K. Constant Coefficient Multipliers for the XC400E, Xilinx Technical Report, 1996
5Wirthlin M J. Constant coefficient multiplication using look-up tables. Journal of VLSI Signal Processing, 21X)4, 36(1): 7-15
6Yoo H, Anderson D V. Hardware-efficient distributed arithmetic architecture for high-order digital filters // ICASSP. Philadelphia, PA, USA, 2005, 0-7803-8874-7/ 05
7Nguyen H T, Chatterjee A. Number-splitting with shift-and- add decomposition for power and hareware optimization in liner DSP synthesis. IEEE transactions on Very Large Scale Integration (VLSI) System, 2000, 8(4): 419-424
8Mirzaei S, Hosangadi A, Kastner R. FPGA implementation of high speed FIR filters using add and shift method // International Conference on Computer Design. Las Vegas, Nevada, USA, 2006
9Mike Foley,Anjan Bose.Object-Oriented Graphical User Interface for Power Systems[J].IEEE Transactions on Power Systems,1993,8(1).
