摘要
A novel dual-feed （DF） low-dropout （LDO） is presented. The DF-LDO adopts dual control loops to maintain the output voltage. The dual control loops include a feedback loop and a feedforward loop. There is an equilibrium point in dual control loops, and the equilibrium point is the output voltage of the DF-LDO. In addition, the transient performance is optimized by adjusting the damping ratio and natural frequency. With a 1 #F decoupling capacitor, the proposed DF-LDO is fabricated in a 0.18 μm CMOS process and its output voltage is 1.5 V. When the workload changes from 100 μA to 100 mA in 100 ns, load regulation of 7 mV for a 100 mA step is achieved, the settling time is 997 ns and the undershoot is 12.8 mV; when the workload changes from 100 mA to 100 μA in 100 ns, the settling time is 249 ns with an imperceptible overshoot.
A novel dual-feed （DF） low-dropout （LDO） is presented. The DF-LDO adopts dual control loops to maintain the output voltage. The dual control loops include a feedback loop and a feedforward loop. There is an equilibrium point in dual control loops, and the equilibrium point is the output voltage of the DF-LDO. In addition, the transient performance is optimized by adjusting the damping ratio and natural frequency. With a 1 #F decoupling capacitor, the proposed DF-LDO is fabricated in a 0.18 μm CMOS process and its output voltage is 1.5 V. When the workload changes from 100 μA to 100 mA in 100 ns, load regulation of 7 mV for a 100 mA step is achieved, the settling time is 997 ns and the undershoot is 12.8 mV; when the workload changes from 100 mA to 100 μA in 100 ns, the settling time is 249 ns with an imperceptible overshoot.
