基于FPGA的高精度IEEE1588时间戳的设计与实现

Design and implementation of high-precision IEEE1588 timestamp based on FPGA

简单介绍了IEEEl588协议的时间同步机制,提出了一种在物理层内部标记时间戳的方案,并采用FPGA设计实现了支持时间戳标记电路的10G Base-R PHY,仿真和测试结果表明这种PHY具有最多一个时钟周期的延迟抖动,极大地降低了网络延时抖动对时间同步精度的影响,满足高精度时间同步的要求。

The paper introduces IEEE1588 protocol time synchronization mechanism simply, time-stamping strategy that is marked in PHY is proposed. 10G Base-R PHY that supports timestamp circuit is designed and implemented based on FPGA. Simulation and test results show that this solution has a maximum delay jitter of one clock cycle, greatly reduces the impact of network delay jitter on time synchronization accuracy and meets high-precision requirements of time synchronization.