基于FPGA的Ethernet Powerlink通信节点的设计与实现

Design and Implementation of Ethernet Powerlink Communication Node Based on FPGA

针对目前运动控制系统对现场总线的实时性要求日益增高这一问题,分别以FPGA+PHY网络芯片、Nios II软核处理器作为基本硬件和软件平台,结合Powerlink开源协议,设计并实现最小循环周期为500的通信节点(从站),从而保证运动控制系统通信的实时性。

Aiming at the motion control system of ifeld bus real-time requirements increasing this problem, the FPGA＋PHY network chip, Nios II processor as the basic hardware and software platform, combined with the open source Powerlink protocol stack, the design and implementation of the minimum cycle for the communication node 500 （slave）, so as to ensure the real-time motion control system communication.