低成本AES错误检测方案的FPGA实现

Low Cost Fault Detection Scheme for AES Using FPGA Implementation

目前,嵌入式加密芯片在信息安全领域所面临的挑战不仅来自理论上的攻击,还存在针对其物理实现的攻击.即使数据加密,仍不能保证传输过程中的正确性和可靠性.而如何在攻击者恶意注入错误攻击之后能够自身检测是当前信息安全领域的研究热点.在研究AES算法的基础上,针对现有具备错误检测功能的AES算法的硬件实现占用电路面积大、应用不灵活等问题,提出一种针对AES加密的错误检测方案,其中优化了在AES实现中资源占用最多的S-盒模块在GF(24)域上的错误检测实现.与已有设计比较发现,本文设计有效减少了S-盒错误检测方案的硬件面积.本文设计方案在Xilinx Virtex-6 FPGA平台上进行了综合仿真验证,结果表明,在不影响检错率的情况下,具有占用硬件面积小、成本低的优点.

Currently,embedded encryption chips in information security field are facing attacks both from theoretical level and physical implementation level. Although data is encrypted during the communication,this still cannot guarantee its correctness and reliability.Howto detect this fault attacks by the attacker becomes one of the hot research topics. This paper proposes a novel fault detection scheme for AES aiming to solve the problems of existing AES implementations,such as inflexibility and large area. Further,we also optimized fault detection for S-box over G F（ 24） field,which is the most area consuming module in AES implementation. Compared with the existing designs,our proposed design effectively reduces the hardware area of fault detection for S-box. Experiment results showthat our proposed design has the advantages of smaller area and lower cost without affecting the error detection rate when ported to Xilinx Virtex-6 FPGA platform.