基于信号机制的硬件多线程实现

Implementation of hardware multithreading based on signal mechanism

目的研究基于可编程逻辑的32位MIPS流水线处理器应用硬件多线程方式的实现。方法首先描述了新的线程管理指令,以使处理器可以支持4个线程;其次通过编写硬件描述语言并进行相应的功能仿真以及后续的时序仿真,确保功能和时序的正确性;最后通过Xilinx ISE对Spartan3e芯片进行综合。结果综合结果显示在逻辑块中多线程占用了25%的开销,最大的部分来自于多个程序计数器、本地状态寄存器和线程切换的相关逻辑。结论通过功能仿真对比,发现4线程处理器的性能相比较单线程有很大提升。

Objective--To investigate the implementation of hardware multithreading based on a 32- bit MIPS programmable logic pipeline processor. Methods--Firstly, new instructions for thread man-agement are described for supporting up to 4 threads; Secondly, through the preparation of hardware description language and the function simulation and subsequent timing simulation, the functional cor- rectness and timing were ensured; Finally, a Spartan-3E logic chip was synthesized through the results obtained by Xilinx-ISE. Results--Comprehensive results indicate the multithreading in a logic element takes up 25% of overhead, with the largest contribution from multiple program counters, local CSR and the logic associated with thread-switching. Conclusion--In functional simulation, the performance of 4 threads processor is improved more than that of single thread processor.