PCIe总线与低速并行总线互连的设计与实现

Design and Realization of the interconnection between PCIe bus and low speed parallel bus

在嵌入式系统中,内部数据访问通常使用低速的并行数据总线,而系统与外部模块数据交换则需要使用较高速率的总线。文章提出了一种可以简易地实现嵌入式系统内部的低速并行总线与外部高速的PCIe串行总线互连方案。

In embedded system, internal data access is achieved by low parallel bus, while data exchanges with external module always use high speed bus. This article proposes an approach that can easily realize the interconnection between low speed parallel bus in embedded system and external high speed serial PCIe bus.